1. Field of the Invention
The present invention relates to a delay circuit and a semiconductor integrated circuit operating in synchronization with a clock. More particularly, it relates to a semiconductor integrated circuit implementing a delay locked loop (DLL) circuit for synchronizing an internal clock signal for use in the interior circuit with an external clock signal supplied from the exterior.
2. Description of the Related Art
Synchronous DRAMs (SDRAMs), double data rate synchronous DRAMs (DDR-SDRAMs), and the like are known as the semiconductor integrated circuits operating in synchronization with a clock. In the semiconductor integrated circuits of this type, the interior circuit is operated in synchronization with the clock signal supplied from the exterior, for data input/output. In general, the semiconductor integrated circuit has a plurality of data output terminals. The output data output from these output terminals has skews in accordance with the wiring length of the signal lines depending on the circuit layout on the chip. The skews relatively increase with higher frequency the clock having. Recently, the skew mentioned above has become a big problem which can not be ignored since SDRAMs and DDR-SDRAMs having an operating frequency over 100 MHz have been developed.
In order to reduce such skews, there has been developed a semiconductor integrated circuit implementing a DLL circuit. The DLL circuit adjusts the phase of an internal clock signal to be used in the interior circuit to a predetermined phase of the reference clock signal supplied from the exterior. Its basic configuration has been disclosed, for example, in Japanese Patent Laid-Open Publication No. Hei 10-112182.
Moreover, there has been proposed a DLL circuit comprising a rough delay circuit having rougher units for delay time adjustment and a fine delay circuit having finer units for delay time adjustment. The DLL circuit of this type can improve the precision of the phase adjustment and reduce jitter in the internal clock signal as well.
FIG. 1 shows an example of the semiconductor integrated circuit implementing the DLL circuit proposed by the present applicant. Incidentally, the circuit shown in FIG. 1 has not publicly known.
This semiconductor integrated circuit comprises: an input buffer 1 for outputting a clock signal CLK accepted from the exterior as an internal clock signal ICLK; a delayed clock generator 2 for generating an internal clock signal ICLK2 delayed by a predetermined time from the internal clock signal ICLK; an output buffer 3 for outputting a data signal DATA read out from a memory cell or the like as an output signal DOUT in synchronization with the internal clock signal ICLK2; a phase control unit 4 for adjusting the phase of the internal clock signal ICLK2 to the phase of the clock signal CLK; and a start signal generator 5 for generating a start signal START for synchronizing the operations of the delayed clock generator 2 and the phase control unit 4.
The delayed clock generator 2 comprises a rough variable delay circuit 6 and a fine variable delay circuit 7.
The rough variable delay circuit 6, constituted by cascading a plurality of delay stages (not shown) having longer delay time, is a circuit for making a rough adjustment to delay time in accordance with the number of delay stages connected. Under the control of a rough delay control circuit 13, the rough variable delay circuit 5 upshifts or downshifts to increase or decrease the number of delay stages connected.
The fine variable delay circuit 7, constituted by cascading a plurality of delay stages (not shown) having shorter delay time, is a circuit for making a fine adjustment to delay time in accordance with the number of these delay stages connected. Under the control of a fine delay control circuit 15, the fine variable delay circuit 7 increases (upshifts) or decreases (downshifts) the number of delay stages connected. The maximum delay time of the fine variable delay circuit 7 is somewhat longer than the delay time of one delay stage in the rough variable delay circuit 6.
The phase control unit 4 comprises frequency dividers 8 and 9, a dummy output buffer 10 equivalent to the output buffer 3, a dummy input buffer 11 equivalent to the input buffer 1, a rough phase comparator 12, the rough delay control circuit 13, a fine phase comparator 14, the fine delay control circuit 15, a stage number setting circuit 16, a stage number detector 17, and a DLL control circuit 18.
The frequency divider 8 divides the frequency of the internal clock signal ICLK to generate an internal clock signal /CLK1, and outputs the same to the rough phase comparator 12 and the fine phase comparator 14. Here, xe2x80x9c/xe2x80x9d employed in the clock signal /CLK1 or the like indicates a logic inversion with respect to the clock signal CLK.
The frequency divider 9 divides the frequency of the internal clock signal ICLK2 to generate an internal clock signal ICLK3, and outputs the same to the dummy output buffer 10. The frequency dividers 8 and 9 have a dividing rate of 1/4, for example. The frequency division of the clock signals ICLK and ICLK2 facilitates the phase comparison at higher frequency as well as reduces the power consumption.
The signal output from the dummy output buffer 10 is supplied to the dummy input buffer 11, and output to the rough phase comparator 12 and the fine phase comparator 14 as an internal clock signal DICLK.
The stage number setting circuit 16 has a delay circuit equivalent to one delay stage in the rough variable delay circuit 6 and a delay circuit equivalent to one delay stage in the fine variable delay circuit 7. The stage number setting circuit 16 always monitors how many stages of the fine variable delay circuit 7 corresponds to the delay time of one delay stage in the rough delay control circuit 6, and outputs the number of stages to the fine delay control circuit 15 and the stage number detector 17 as a maximum stage number signal J2. The maximum stage number signal J2 varies with the operating voltage and the ambient temperature of the semiconductor integrated circuit.
The stage number detector 17 has the function of receiving a stage number signal J1, which is the number of delay stages used in the fine variable delay circuit 7, and the maximum stage number signal J2. It respectively outputs an overflow signal OF and an underflow signal UF when the stage number signal J1 becomes the maximum stage number signal J2 and the stage number signal J1 reaches the minimum value.
The DLL control circuit 18 receives a phase coincidence signal JSTR from the rough phase comparator 12, receives the overflow signal OF and the underflow signal UF from the stage number detector 17, and outputs select signals S1 and S2, a shift-up signal UP, and a shift-down signal DOWN. The DLL control circuit 18 activates the select signal S1 and inactivates the select signal S2 when the phase coincidence signal JSTR is inactive, and inactivates the select signal S1 and activates the select signal S2 when the phase coincidence signal JSTR is active. The DLL control circuit 18 also outputs the shift-up signal UP to the rough phase comparator 12 on receiving the overflow signal OF, and outputs the shift-down signal DOWN to the rough phase comparator 12 on receiving the underflow signal UF.
The rough phase comparator 12 receives the activated select signal S1, compares the phases of the internal clock signal /CLK1 and the internal clock signal DICLK, and outputs the comparison result to the rough delay control circuit 13. The rough phase comparator 12 activates the phase coincidence signal JSTR when the internal clock signal DICLK and the internal clock signal /CLK1 coincide with each other in phase, upshifts the rough variable delay circuit 6 on receiving the shift-up signal UP, downshifts the rough variable delay circuit 6 on receiving the shift-down signal DOWN, and outputs a reset signal MIN and a set signal MAX respectively when upshifting and downshifting the rough variable delay circuit 6.
The rough delay control circuit 13 upshifts/downshifts the rough variable delay circuit 6 based on the comparison result from the rough phase comparator 12, for delay time adjustment. That is, the rough delay control circuit 13 increments by one the number of delay stages connected when the internal clock signal DICLK leads the internal clock signal /CLK1 in phase, and decrements by one the number of delay states connected when the internal clock signal DICLK delays from the internal clock signal /CLK1 in phase.
The fine phase comparator 14 is a circuit for receiving the activated select signal S2, comparing the phases of the internal clock signal DICLK and the internal clock signal /CLK1, and outputting the comparison result to the fine delay control circuit 15.
The fine delay control circuit 15 upshifts/downshifts the fine variable delay circuit 7 based on the comparison result from the fine phase comparator 14, for delay time adjustment. That is, the fine delay control circuit 15 increments by one the number of delay stages connected when the internal clock signal DICLK leads the internal clock signal /CLK1 in phase, and decrements by one the number of delay stages connected when the internal clock signal DICLK delays from the internal clock signal /CLK1 in phase. The fine delay control circuit 15 also minimizes the number of delay staged connected in the fine variable delay circuit 7 on receiving the reset signal MIN, makes the number of delay stages connected in the fine variable delay circuit 7 equal to the maximum stage number signal J2 on receiving the set signal MAX, outputs the current number of delay stages connected in the fine variable delay circuit 7 as the stage number signal J1.
The start signal generator 5 receives the internal clock signal ICLK, and outputs a start signal STT. This circuit activates the start signal STT in synchronization with the fall of the internal clock signal ICLK upon the release of a reset signal /RESET. The delay clock generator 2 and the frequency dividers 8, 9 start to operate on receiving the activation of the start signal STT.
FIG. 2 is a flowchart showing the control procedure of the phase adjustment to be performed by the above-described respective circuits. The phase adjustment control is started by the release of the reset signal /RESET.
For a start, at step S1 is executed an initial setup. The stage number setting circuit 16 shown in FIG. 1 judges how many stages of the fine variable delay circuit 7 a delay stage of the rough variable delay circuit 6 corresponds to in delay time, and outputs the result as the maximum stage number signal J2. Besides, the phase control unit 4 is initialized so that the numbers of delay stages connected in the rough variable delay circuit 6 and the fine variable delay circuit 7 are set to initial values. The DLL control circuit 18 activates the select signal S1, and inactivates the select signal S2.
Next, the initial adjustment of the rough variable delay circuit 6 is performed at steps S2-S5.
At step S2, the phase control unit 4 sets the frequency dividers 8 and 9 at 1/4 in dividing rate. The frequency divider 8 receives the internal clock signal ICLK, and outputs the divided internal clock signal /CLK1. The frequency divider 9 receives the internal clock signal ICLK2, and outputs the divided internal clock signal ICLK3.
At step S3, the rough phase comparator 12 compares the phases of the internal clock signal /CLK1 and the internal clock signal DICLK, and outputs the comparison result to the rough delay control circuit 13. Here, the fine phase comparator 14, receiving the inactivated select signal S2, stops operating.
At step S4, the rough phase comparator 12 activates the phase coincidence signal JSTR when the signals compared in the rough phase comparator 12 coincide with each other in phase. The DLL control circuit 18, receiving the phase coincidence signal JSTR, inactivates the select signal S1 and activates the select signal S2. Then, the procedure shifts to step S6. If the signals compared in the rough phase comparator 12 do not coincide with each other in phase, then the procedures shifts to step S5.
At step S5, the rough delay control circuit 13 upshifts/downshifts the rough variable delay circuit 6 in accordance with the comparison result from the rough phase comparator 12, for delay time adjustment. Then, the procedure returns to step S3.
Next, at steps S6-S15 is performed the phase adjustment using the rough variable delay circuit 6 and the fine variable delay circuit 7.
Initially, at step S6, the fine phase comparator 14 compares the phases of the internal clock signal /CLK1 and the internal clock signal DICLK, and outputs the comparison result to the fine delay control circuit 15. Here, the rough variable delay circuit 6, receiving the inactivation of the select signal S1, stops operating.
At step S7, if the signals compared in the fine phase comparator 14 coincide with each other in phase, the procedure returns to step S6. If the internal clock signal DICLK leads the internal clock signal /CLK1 in phase, the procedure shifts to step S8. If the internal clock signal DICLK delays from the internal clock signal /CLK1 in phase, the procedure shifts to step S12.
At step S8, the stage number detector 17 compares the stage number signal J1 with the maximum stage number signal J2. If the stage number signal J1 is equal to the maximum stage number signal J2, then carry-over processing is judged as necessary, and the procedure shifts to step S10. If the stage number signal J1 is smaller than the maximum stage number signal J2, then the carry-over processing is judged as unnecessary, and the procedure shifts to step S9.
At step S9, the fine delay control circuit 15 upshifts the fine variable delay circuit 7 by one stage to delay the internal clock signal ICLK2 in phase.
At step S10, the stage number detector 17 outputs the overflow signal OF. The DLL control circuit 18 receives the overflow signal OF, and outputs the shift-up signal UP. The rough phase comparator 12 receives the shift-up signal UP, upshifts the rough variable delay circuit 6 by one stage, and outputs the reset signal MIN.
At step S11, the fine delay control circuit 15 receives the reset signal MIN, and set the number of delay stages connected in the fine variable delay circuit 7 to the minimum.
After the execution of step S9 or S11, the procedure returns to step S6.
On the other hand, at step S12, the stage number detector 17 examines the stage number signal J1 for the minimum value. If the stage number signal J1 has the minimum value, then carry-down processing is judged as necessary, and the procedure shifts to step S14. If the stage number signal J1 does not have the minimum value, then the carry-down processing is determined unnecessary, and the procedure shifts to step S13.
At step S13, the fine delay control circuit 15 downshifts the fine variable delay circuit 7 by one stage to advance the internal clock signal ICLK2 in phase.
At step S14, the stage number detector 17 outputs the underflow signal UF. The DLL control circuit 18 receives the underflow signal UF, and outputs the shift-down signal DOWN. The rough phase comparator 12 receives the shift-down signal DOWN, downshifts the rough variable delay circuit 6 by one stage, and outputs the set signal MAX.
At step S15, the fine delay control circuit 15 receives the set signal MAX, and set the number of delay stages connected in the fine variable delay circuit 7 to the maximum.
After the execution of step S13 or S15, the procedure returns to step S6.
Then, the phase adjustment is repeatedly performed with intervals of the delay time of a delay stage in the fine variable delay circuit 7. That is, the phase control unit 4 makes rough phase adjustments by using the rough delay control circuit 13, and then makes fine phase adjustments by using the fine delay control circuit 15. The phase of the internal clock signal DICLK is thus adjusted to the phase of the internal clock signal /CLK1.
FIG. 3 shows the timing for the essential signals in phase adjustments. FIG. 3 shows a state in which a phase adjustment is performed so that the internal clock signal /CLK1 and the internal clock signal DICLK coincide with each other in phase.
The start signal STT is activated in synchronization with the fall of the internal clock signal ICLK after the reset signal /RESET is released off to low level (FIG. 3(a)). The output of the internal clock signal ICLK delays from the rise of the clock signal CLK by the delay time T1 of the input buffer 1 shown in FIG. 1 (FIG. 3(b)). The internal clock signal ICLK is frequency-divided to a quarter by the frequency divider 8, and output as the internal clock signal /CLK1 delayed by the delay time T2 of the frequency divider 8 (FIG. 3(c)). The output of the internal clock signal ICLK2 delays from the rise of the internal clock signal ICLK by the delay time T3 of the delayed clock generator 2 (FIG. 3(d)). The frequency of the internal clock signal ICLK2 is divided to a quarter by the frequency divider 9, and output as the internal clock signal ICLK3 delaying from the delay time T2 of the frequency divider 9 (FIG. 3(e)) The frequency dividers 8 and 9 have the same delay time T2. Therefore, the delay of the internal clock signal ICLK3 to the internal clock signal /CLK1 is identical with the delay time T3 of the delayed clock generator 2 (FIG. 3(f)). The internal clock signal ICLK3 is output as the internal clock signal DICLK delaying by the delay time T4 of the dummy output buffer 10 and the dummy input buffer 11 (FIG. 3(g)). The delay time T4 equals to the sum of the delay times of the input buffer 1 and the output buffer 3.
Accordingly, in a state where the internal clock signal /CLK1 and the internal clock signal DICLK coincide with each other in phase, a half cycle of the internal clock signal /CLK1 (=two cycles of the clock signal CLK) becomes equal to the sum of the delay time T3 from the delayed clock generator 2 and the delay time T4 from the input buffer 1 and the output buffer 3 (FIG. 3(h)). This total time T3+T4 is identical with the time elapsing from the supply of the clock signal CLK to the output of the output data signal DOUT. Consequently, the phase of the output data signal DOUT output from the output buffer 3 coincides with the phase of the clock signal CLK (FIG. 3(i)).
In the cases where the DLL control circuit 18 judges xe2x80x9ccarry over xe2x80x9d and xe2x80x9ccarry downxe2x80x9d at steps S8 and S12 shown in FIG. 2, the phase control unit 4 executes the steps S10, S11 and the steps S14, S15, respectively. Here, if the internal clock signal ICLK varies during the procedures of the steps S10 and S11 for example, then there might occur a large shift in the timing of the internal clock signal ICLK2. On this account, the procedures of the steps S10 and S11, as well as those of the steps S14 and S15, need to be executed continuously during a high-level period or a low-level period of the internal clock signal ICLK. In other words, on the occasions of carry-over and carry-down, the shift operation to the rough variable delay circuit 6 and the set/reset operation to the fine variable delay circuit 7 need to be performed continuously during a high-level period or a low-level period of the internal clock signal ICLK.
The timing margins necessary for such control, however, decrease with increasing frequency of the clock signal CLK. In particular, those semiconductor integrated circuits at the frequency of the clock signal CLK exceeding 100 MHz have increasing difficulties with such control.
Besides, in the semiconductor integrated circuit described above, the stage number setting circuit 16 judges the number of stages of the fine variable delay circuit 7 one stage in the rough variable delay circuit 6 corresponds to in delay time. Comprising the circuit equivalent to the delay stage in the rough variable delay circuit 6, the stage number setting circuit 16 has an error with respect to the actual delay time of one delay stage in the rough variable delay circuit 6. This error can cause jitter in the internal clock signal ICLK2.
Moreover, in the semiconductor integrated circuit described above, the clock signals divided by the frequency dividers 8 and 9 are compared by the rough phase comparator 12 and the fine phase comparator 14. However, when the semiconductor integrated circuit is supplied with a clock signal of lower frequency, the rough variable delay circuit 6 requires a greater number of delay stages, thereby producing a problem of increased circuit scale. If the dividing rates of the frequency dividers 8 and 9 are lowered to reduce the number of delay stages, the rough phase comparator 12 and the fine phase comparator 14 become unstable in operation when a clock signal CLK of higher frequency is supplied thereto. In addition, the frequency of phase comparisons becomes greater, thereby increasing the power consumption.
Meanwhile, a phase adjustment circuit has been proposed which comprises: a delay circuit constituted by cascading four (or eight) delay stages variable in delay time; interpolators for receiving adjacent two clock signals among the clock signals output from the individual delay stages, and generating an internal clock signal; a phase comparator for comparing the phases of the internal clock signal and an external clock signal; a control circuit for controlling the delay circuits and the interpolators based on the comparison results from the phase comparator.
In this phase adjustment circuit, the delay circuit adjusts the respective delay stages in delay time according to the frequency of the external clock signal, and outputs clock signals whose phases are shifted by 90xc2x0 (or 45xc2x0) from one another. The interpolators receive adjacent two clock signals, and generate clock signals having a phase between those of the clock signals. Then, the phase comparator and the control circuit control the delay circuits and the interpolators so that the internal clock signal and the external clock signal coincide with each other in phase.
The phase adjustment circuit of this type, however, has a problem in that it can only make a phase adjustment within a single cycle of the external clock signal. This means a narrower range of phase adjustment particularly in the case where an external clock signal of higher frequency is supplied to the semiconductor integrated circuit. Moreover, because of containing unnecessary elements such as CR time constant circuits so as to allow the delay time adjustments, the delay stages are greater in layout size.
An object of the present invention is to provide a delay circuit capable of precisely adjusting the delay time of a clock signal to be delayed.
Another object of the present invention is to provide a semiconductor integrated circuit capable of always performing proper phase comparisons independent of the frequency of a clock signal.
Another object of the present invention is to prevent the occurrence of jitters of an internal clock signal during phase adjustment.
Another object of the present invention is to decrease the number of times phase comparisons are performed to reduce the time required for making the phases coincide.
Another object of the present invention is to reduce the power consumption of circuits necessary for phase comparisons.
According to one of the aspects of the delay circuit in the present invention, the delay circuit comprises a plurality of interpolators connected in cascade. Each of the interpolators receives a reference clock signal and a clock signal output from the preceding interpolator. One of the interpolators operates as a phase adjustment circuit for generating an adjustment clock signal whose transition edge is between the transition edge of the reference clock signal and the transition edge of the clock signal. A predetermined number of interpolators subsequent to the phase adjustment circuit respectively operate as delay stages for generating clock signals delayed by a predetermined time from the clock signals output from the preceding interpolator. Thus, a delayed clock signal delayed from the reference clock signal by a predetermined time is generated.
In this delay circuit, the delayed clock signal is adjusted in delay time by using the interpolators; this enables the minimum unit of the adjustment to be made smaller. In other words, the delayed clock signal can be precisely adjusted.
According to another aspect of the delay circuit in the present invention, operating only those interpolators necessary for generating the delayed clock signal results in reducing the power consumption.
According to another aspect of the delay circuit in the present invention, the delay time of the delayed clock signal is adjusted in two steps; switch controlling the interpolators and phase controlling the phase adjustment circuit. Therefore, the adjustment for shifting the delay time of the delayed clock signal is quickly performed.
According to one of the aspects of the semiconductor integrated circuit in the present invention, clock signals such as an internal clock signal are adjusted in delay time with ease and precision.
According to another aspect of the semiconductor integrated circuit in the present invention, a phase comparator compares the phase of the reference clock signal with the phase of the delayed clock signal. A control circuit supplies the ratio information to the phase adjustment circuit based on the comparison result from the phase comparator and makes the phase of the reference clock signal coincide with the phase of the delayed clock signal. Since the phase of the delayed clock signal is adjusted by controlling the delay circuit including the plurality of interpolators, the minimum unit of the fine adjustment can be made small. That is, the phase adjustment is performed with reliability even in the semiconductor integrated circuits supplied with the reference clock signal of higher frequency.
According to another aspect of the semiconductor integrated circuit in the present invention, the ratio information is easily set by a shift register or a counter.
According to another aspect of the semiconductor integrated circuit in the present invention, the control circuit, at the beginning of a phase comparison, roughly adjusts the phase of the delay clock signal in accordance with the comparison result from the phase comparator. After the time corresponding to the phase difference between the delayed clock signal and the reference clock signal becomes equal to or shorter than the delay time of the interpolators operating as the delay stages, the control circuit supplies the ratio information to the phase adjustment circuit to finely adjust the delayed clock signal in phase. Adjusting the phase of the delayed clock signal in the separate steps of the rough adjustment and the fine adjustment makes it possible that the phase of the delayed clock signal coincide with the phase of the reference clock signal at a smaller number of times of phase comparisons.
According to another aspect of the semiconductor integrated circuit in the present invention, the control circuit judges the phase difference between the delayed clock signal and the reference clock signal to be equal to or shorter than the delay time of the delay stage, based on the reversal of the phases of the delayed clock signal and the reference clock signal. Then, the fine adjustment starts by the phase adjustment circuit. It is possible to judge the reversal of phases with ease by a simple circuit such as a latch, so that the circuit can be reduced in size.
According to another aspect of the semiconductor integrated circuit in the present invention, the interpolators are connected with independent power supply lines. Therefore, it is possible to prevent the clock signals output from the interpolators from varying in phase affected by the other circuits. In addition, supplying lower voltages to the interpolators compared with the other circuits, leads to reducing the power consumption.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit further comprises a start signal generator for activating a start signal in synchronization with the reference clock signal at the beginning of the phase comparison. Therefore, the control circuits can be synchronized with one another at the beginning of the phase comparison so that the phase comparison can always be started at a predetermined timing.
According to another aspect of the semiconductor integrated circuit in the present invention, the start signal generator activates the start signal in synchronization with the falling edge of the reference clock signal. Therefore, the high-level period of the reference clock signal is masked by the start signal so that the occurrence of hazard of the reference clock signal can be prevented and the delay circuit can be stably operated.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises frequency dividers for respectively dividing the frequencies of the reference clock signal and the delayed clock signal. The phase comparator is supplied with the reference clock signal and the internal clock signal having their frequencies divided by the frequency dividers. Therefore, the phase comparator can be operated with reliability even when the reference clock signal is supplied at higher frequency. Decreasing the frequency the phase comparison is performed results in reducing the power consumption.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit further comprises a start signal generator for activating a start signal in synchronization with the reference clock signal at the beginning of the phase comparison. The frequency dividers start operating in response to the activation of the start signal and then respectively start outputting the divided reference clock signal and the divided delayed clock signal after a predetermined number of clocks. Therefore, it is possible to reduce the maximum value of the phase difference between the reference clock signal and the delayed clock signal supplied to the phase comparator when the reference clock signal has certain frequency. As a result, the number of times phase comparisons are performed during the rough adjustment can be decreased as well as the number of the interpolators.
According to another aspect of the semiconductor integrated circuit in the present invention, the number of clocks, from the reception of the activation of the start signal to the beginning of the output of the divided reference clock signal and the delayed clock signal, is set in accordance with the frequency of the reference clock signal. This makes it possible to reduce the number of times of phase comparisons required for the phase adjustment.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit further comprises a mode register for setting a number of wait clocks. Therefore, the number of wait clocks can be easily set in accordance with the frequency of the reference clock signal by modifying the mode register at such occasions as the power is switched on.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit further comprises a fuse for setting the predetermined number of clocks. This enables easy and reliable setting of the predetermined number of clocks by blowing the fuse in accordance with device specifications (frequency) in the fabrication process.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises control terminals for setting the predetermined number of clocks. Therefore, the control terminals can be used as test terminals for the evaluation of products. The control terminals are connected with power supply lines or ground lines to set the predetermined number of clock signals. By using the control terminals as external terminals, the predetermined number of clocks is set on board in accordance with the clock frequency of the system mounting the semiconductor integrated circuit.
According to another aspect of the semiconductor integrated circuit in the present invention, the semiconductor integrated circuit comprises a main delay circuit, a sub delay circuit, a selecting circuit, a phase comparator, and a control circuit.
The main delay circuit comprises a plurality of interpolators connected in cascade. Each of the interpolators receives a reference clock signal and a clock signal output from the preceding interpolator. One of the interpolators operates as a phase comparator for generating an adjustment clock signal whose transition edge is between the transition edge of the reference clock signal and the transition edge of the clock signal. A predetermined number of interpolators subsequent to the phase adjustment circuit respectively operate as delay stages for generating a clock signal delayed by a predetermined time from the clock signal output from the preceding interpolator. The main delay circuit thus generates a delayed clock signal delayed from the reference clock signal by a predetermined time.
The sub delay circuit comprises a second interpolator for generating in accordance with the ratio information a second delayed clock signal whose transition edge is between the transition edge of the reference clock signal and the transition edge of the clock signal.
The selecting circuit outputs the delayed clock signal output from the main delay circuit or the second delayed clock signal from the sub delay circuit as an internal clock signal. In addition, the selecting circuit selects the second delayed clock signal output from the sub delay circuit when a predetermined interpolator at the front or the back side of the main delay circuit operates as the phase adjustment circuit.
The phase comparator compares the phase of the reference clock signal with the phase of the internal clock signal. The control circuit supplies the ratio information to the phase adjustment circuit in the main delay circuit and the interpolators in the sub delay circuit based on the comparison result from the phase comparator and makes the phase of the reference clock signal coincide with the phase of the delayed clock signal.
Here, comprising the sub delay circuit makes it possible to temporarily operate the second interpolator of the sub delay circuit as the phase adjustment circuit when operating the interpolator at one side of the main delay circuit and then the interpolator at the other side thereof as the phase adjustment circuit. Therefore, it is possible to switch the interpolators of the main delay circuit while the second interpolator of the sub delay circuit adjusting the phase. At this time, the selecting circuit selects the second delayed clock signal output from the sub delay circuit. Accordingly, the internal clock signal is not affected by switching the interpolators. This consequently prevents the occurrence of jitters of the internal clock signal.
According to another aspect of the semiconductor integrated circuit in the present invention, the sub delay circuit can make phase adjustment in the wider phase range than the interpolators in the main delay circuit. This allows sufficient time margin for the selecting circuit to select each of the delayed clock signals, thereby realizing stable phase adjustment.
According to another aspect of the semiconductor integrated circuit in the present invention, the interpolators at both sides of the main delay circuit are used in the same phase region (for example, 0-90xc2x0). As a result, when making the phase adjustment, for example, from 350xc2x0 to 370(=10)xc2x0, the interpolator at one side makes the adjustment while the interpolator on the other side prepares for an adjustment, whereby the interpolators are smoothly switched.
According to another aspect of the semiconductor integrated circuit in the present invention, the interpolators are connected with independent power supply lines. This prevents the phase fluctuation of the clock signals output from the interpolators due to the influences of the other circuits. Moreover, supplying lower voltages to the interpolators can reduce the power consumption.
According to another aspect of the semiconductor integrated circuit in the present invention, an adjustment delay circuit comprises a plurality of third interpolators connected in cascade. The adjustment circuit adjusts the maximum delay time of the interpolators in the main delay circuit and the second interpolator in the sub delay circuit to a value which is one fraction of an integer of the cycle of the reference clock signal, by adjusting the third interpolators in the adjustment delay circuit. Accordingly, when the maximum delay time of one interpolator is adjusted to a value, for example, a fourth (90xc2x0) of the cycle of the reference clock signal, the phase value equivalent to one cycle of the reference clock can be adjusted by four interpolators. In this example, at least four interpolators are used for adjusting the phase of the reference clock signal because a shift of 10xc2x0 and a shift of 370xc2x0 in phase are relatively the same. Accordingly, it is possible to precisely adjust the phases by fewer interpolators.
According to another aspect of the semiconductor integrated circuit in the present invention, the second phase comparator in the adjustment circuit compares the phase of the reference clock signal with the phase of an output clock signal output from the adjustment delay circuit. The adjustment circuit adjusts the maximum delay time of the third interpolators in the adjustment delay circuit to a value which is one fraction of an integer or a multiple of the cycle of the reference clock signal, based on the comparison result from the phase comparator. Then, the maximum delay time of the interpolators in the main delay circuit and the second interpolator in the sub delay circuit are indirectly adjusted to a value which is one fraction of an integer or a multiple of the cycle of the reference clock signal, by adjusting the adjustment delay circuit. Accordingly, the adjustment by the adjustment circuit does not affect the interpolators in the main delay circuit and the second interpolator in the sub delay circuit, so that these interpolators can perform stable operations.
According to another aspect of the semiconductor integrated circuit in the present invention, the adjustment circuit adjusts the third interpolators in the adjustment delay circuit, which are identical to the interpolators in the main delay circuit and the second interpolator in the sub delay circuit. This facilitates the adjustment to the phase of the reference clock signal.
According to another aspect of the semiconductor integrated circuit in the present invention, the number of interpolators in the main delay circuit is more than the number of third interpolators in the adjustment delay circuit. For example, the adjustment delay circuit is comprised of four third interpolators and the maximum delay time of the third interpolators is set at a value, a fourth (90xc2x0) of the cycle of the reference clock signal. In this case, the main delay circuit is comprised of five interpolators, having the range of phase adjustment at 450xc2x0. On this account, the two interpolators at both sides of the main delay circuit can be used in the same phase region (for example, 0-90xc2x0). As a result, when making the phase adjustment from 350xc2x0 to 370(=10)xc2x0, for example, the interpolator at one side can make the adjustment while the interpolator at the other side prepares for an adjustment, thereby allowing the smooth switching of the interpolators.
According to another aspect of the semiconductor integrated circuit in the present invention, when the adjustment delay circuit sets the delay time equal to one cycle of the reference clock signal, the interpolators at both sides of the main delay circuit can be used in the same phase region (for example, 0-90xc2x0). Consequently, the interpolators are smoothly switched as mentioned above.
According to another aspect of the semiconductor integrated circuit in the present invention, the phase adjustment by the control circuit is performed after the adjustment circuit adjusting the maximum delay time, that is, after setting the maximum delay time of the main delay circuit and the sub delay circuit. This prevents the occurrence of jitters of the delayed clock signal affected by the adjustment circuit.
According to another aspect of the semiconductor integrated circuit in the present invention, the control circuit roughly adjusts the phase of the internal clock signal in accordance with the comparison result from the phase comparator at the beginning of a phase comparison. After the time corresponding to the phase difference between the delayed clock signal and the reference clock signal becomes equal to or shorter than the maximum delay time of the interpolators, the control circuit supplies the ratio information to the phase adjustment circuit in accordance with the comparison result from the phase comparator so as to finely adjust the phase of the internal clock signal. Separately performing the rough and the fine phase adjustments to the internal clock signal makes it possible that the phase of the delayed clock signal coincide with the phase of the reference clock signal at a smaller number of times of phase comparisons.
According to another aspect of the semiconductor integrated circuit in the present invention, the control circuit judges the phase difference between the reference clock signal and the internal clock signal to be equal to or shorter than the maximum delay time of the interpolators based on the reversal of the phases of the reference clock signal and the internal clock signal. Then, the phase adjustment circuit starts the fine adjustment. It is possible to easily judge the reversal of the phases by a simple circuit such as a latch, whereby the circuit can be reduced in size.
According to another aspect of the semiconductor integrated circuit in the present invention, when the ratio information is set at the central value, all the interpolators that can be switched to the phase adjustment circuit, delay the reference clock signal by the same amount of time. This equalizes the phase variation of the internal clock signal when the interpolators switched to the phase adjustment circuit.